《Low power design essential》读后笔记(二)

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chapter 2

1. sub-100 nm

leakage behavior of the transistor

variability

innovative devices

a linear relationship exists in relation to voltage and current;
the threshold voltage is dependent on both the channel length and applied voltages.

a linear relationship exists in relation to voltage and current;
the threshold voltage is dependent on both the channel length and applied voltages.

2. I_D-V_{DS}

velocity-saturation effect

decrease in output resistance of the device in saturation
Reason:

• channel-length modulations * 也称为 * gate-length induced effects * ，它与 * Vt * 的变化密切相关；* DIBL*（* Drain-Induced Barrier Lowering*）现象不仅会影响电路性能还与 * Substrate Current Body Effect* 有密切关联；* SCBE* 是指 * Substrate Current Body Effect* 的表现形式

Model:

I_{Dsat} = \upsilon_{Sat}WC_{ox}\frac{(V_{GS}-V_{TH})^2}{(V_{GS}-V_{TH})+E_CL} E_C represents the critical electric field.

the unified modeling framework is characterized by a piecewise function defining the drain current (I_D) under different voltage conditions. Specifically, when the gate-source voltage (V_GT) is less than or equal to zero, the drain current equals zero. For positive gate-source voltages, I_D is determined by a complex expression involving width-to-length ratio (W/L), drain-source voltage (V_DS), and a modulation factor that depends on both the overdrive voltage and body effect. The relationship between gate threshold voltage (V_TH) and gate-source voltage (V_GS) is defined as wherein the gate threshold voltage equals the substrate-induced potential minus the threshold potential at zero bias. The threshold potential itself incorporates both material properties and device geometry through its dependence on surface potential and oxide thickness.

V_{Dsat} is a fixed voltage

alpha model
I_{DS} = \frac{W}{2L}\mu C_{ox}(V_{GS}-V_{TH})^{\alpha}

3. Threshold

use the extrapolation technique

not a constant V_{SB} can be used to control V_{TH}

The foremost is the body-bias or back-bias effect \gamma

channel length (short channel) shorter channel, smaller threshold

solutions: “halo implants” increases the threshold

DIBL: drain voltage influences the threshold
V_{TH} = V_{TH0}-\lambda_d V_{DS}

4. sub-threshold drain-source effects

below 180 nm level

Reason:

The drain-source voltage (V_{GS}) has an exponential relationship, which is also affected by the parameters \gamma_d and \lambda_d. In the case where the gate-source voltage (V_G) is negative, the phenomenon known as Gate-Induced Drain Leakage (GIDL) occurs. NMOS devices exhibit larger values compared to PMOS devices. GIDL has a relatively minor effect compared to DIBL.

5. gate leakage

below 100 nm level

Typically, scaling the gate oxide, commonly known as SiO₂, correspondingly contributes to a significant reduction in the gate resistance of the transistor.

Reason:

Fowler-Nordheim(FN) tunneling

direct-oxide tunneling dominant

exponentially with respect to both of these parameters

solutions:

• stop or slow down the scaling of oxide thickness

example:

keep the current the same while increase the thickness of the gate

k^{’} = \mu C_{g} = \mu \epsilon/t_g

high-k gate replace SiO2 with high-k material

“equivalent oxide thickness” (EOT) = T_g \times (\epsilon_{ox}/\epsilon_{g})

6. temperature influence

temperature rises, mobility reduces, V_{TH} reduces.

I_{on} decreases, I_{off} increases

7. variability

worst-case corners(FF, SS, FS, SF) cause flunctations

low-power design: lower V_{DD}/V_{TH}, smaller SNR worse variability

Reason:

physical

manufacturing dominant

environmental solution: package

operational

8. innovations:

strained silicon dioxide enhances the charge carrier mobility in CMOS SiGe PMOS devices compared to NMOS devices.

V_{TH} increases at the same time , I_{on} increase, I_{off} decrease

Silicon-on-insulator (SOI) have thin silicon layer

junction capacitances are reduced power saving

higher sub-threshold slope factor reduce leakage

sensitivity to soft errors

example: PD-SOI(partially-depleted) FD-SOI(fully-depleted)

FD-SOI with a buried gate control threshold

The FinFET technology enhances the channel length ratio of the electronic device's SOI substrate.

example: Double-gated(DG) MOSFET Back-gated(BG) MOSFET

CNT(carbon-nanotube)

I-MOS

MEMS