全志r11运行鸿蒙,全志R11芯片怎么样?全志R11处理器参数

R11标志着Allwinner在智能硬件处理器领域的最新进展，并采用了一个基于单ARM架构的处理器，在运行速度上达到每秒一万二千次。

CortexTM-A7 CPU，并支持多个外围设备。

CPU

ARM Cortex-A7 MP1 Processor incorporates Thumb 2 technology, which supports highly efficient Single Instruction Multiple Data (SIMD) operations.

instruction for acceleration of media and

signal processing

functions Supports Large Physical Address

Implementation of LPAE, the VFPv4 Floating-Point Unit is designed with a capacity of 32KB for both the Level 1 Instruction Cache and the Level 1 Data Cache.

cache 128KB L2 cache

Memory Subsystem Boot ROM

Internal on-chip memory Supports system boot from the following

devices: - SPI NOR Flash - SPI NAND Flash - SD/TF Card - eMMC Can download system code via USB OTG

SDRAM

Integrated embedded DRAM, equipped with DDR2 technology within the R11 architecture, operating at a maximum frequency of 400 MHz, incorporates support for Memory Dynamic Frequency Scaling (MDFS).

SD/MMC

External off-chip memory and storage

该设备支持双路SD/MMC控制器，并配备四分之一位数据总线接口以实现与eMMC标准规范V4.41版本的有效通信；该系统遵循SD物理层协议以确保数据传输的可靠性

specification V2.0, SDIO card specification

Supports hardware CRC generation and error

detection Block size from 1 to 65535 bytes

System Peripheral Timer

Three on-chip timers with interrupt-based

operation One watchdog to generate reset signal or

triggering the 33-bit audio/video synchronization (AVS) counter at a rate of 24 MHz or accepting an internal OSC clock input

High Speed Timer

Two high-speed timer counters with a maximum resolution of 56 bits

than other timers

GIC

Supports 16 Software Generated Interrupts(SGIs), 16 Private

Peripheral Interrupts(PPIs) and 125 Shared

Peripheral Interrupts(SPIs)

DMA

该系统最多支持8通道DMA技术；灵活的数据总线宽度可达8、16或32位；能够执行基于内存的数据传输类型；并支持线性和IO地址模式的各种数据转移类型

memory-to-peripheral, peripheral-to-memory

CCU

nine phase-locked loops, each equipped with a self-contained RC oscillator integrated on the chip, along with a 24 MHz external oscillator and a 32.768 kHz external oscillator for reliable clock management, incorporating mechanisms such as clock gating and frequency modulation within the device to ensure optimal performance

modules, clock reset, clock generation, clock division

PWM

Two PWM channels are capable of generating two types of waveform: continuous waveform as well as

pulse waveform 0% to 100% adjustable duty cycle Up to 24MHz output frequency

RTC

Time, calendar counters for second, minutes, hours, day, week, months as well as year including leap years.

year generator Alarm:general alarm and weekly alarm

LRADC

6-bit分辨率设备具备锁定键和连续键支持，并支持单个键、正常键和连续键功能

Crypto Engine

Supports AES 128/192/256-bit with ECB,CBC,CTS,CTR

该加密模式支持使用 DES/TDES 加密算法配合 ECB、CBC 和 CTR 格式进行数据加密；同时支持 SHA1 和 MD5 加密算法，并采用具有 160 位输出长度的硬件级随机数生成器（PRNG），其种子值长度为 175 位

Display Subsystem DE2.0

Output size up to 1024x1024 Supports three alpha blending channel for main

display is designed to support four separate overlay layers across each channel, which is independent.

scale Supports potter-duff compatible blending

operation Supports input format

YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565

Display Output

Supports LVDS interface with single link, up to

1024x768@60fps Supports RGB interface with DE/SYNC mode, up to

1024x768@60fps Supports serial RGB/dummy RGB/CCIR656 interface, up to

800x480@60fps Supports i80 interface with 18/16/9/8 bit, support TE, up to

800x480@60fps Supports pixel format: RGB888, RGB666 and

RGB565 Dither function from RGB666/RGB565 to

RGB888 Gamma correction with R/G/B channel independence

Video Engine Video Decoding

Supports video decoder for H.264 and

JPEG/MJPEG Supports H.264 BP/MP/HP up to 1080p@30fps Supports H.264 output formats

:NV21,NV12,YU12,YV12 Supports JPEG/MJPEG up to 1080p@30fps

Video Encoding

Supports H.264 video encoding up to

720p@60fps JPEG baseline: picture size up to 8192x8192 Supports input picture size up to 4800x4800 Supports input format:

YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY支持Alpha混合技术，并且实现了指纹生成功能；该系统能够灵活配置从1/16到64的任意非整数缩放比例

ratio Supports rotated input

Image Subsystem Image Input

Supports 8/10-bit CMOS sensor parallel

interface Supports 8-bit CCIR656 protocol for NTSC and

PAL Supports ITU-R BT 1120 protocol for HD-CIF

system Supports 16-bit interface with separate

syncs MIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2

v1.0 Supports MIPI-CSI2 1/2 data lanes

configuration Supports Format:

- YUV422-8/10 bits - YUV420-8/10 bits(for MIPI-CSI2 only) - RAW-8/10 bits - RGB888/RGB565(for MIPI-CSI2 only)

Performance: - Still capture resolution up to 5M with parallel

interface - Video capture resolution up to 1080p@30fps with parallel

interface - Still capture resolution up to 5M with MIPI-CSI2

interface - Video capture resolution up to 1080p@30fps with MIPI-CSI2

interface - MIPI-DPHY maximum data rate up to 1Gbps per lane

ISP

Supports input formats:8/10-bit RAW RGB,8-bit

YCbCr Supports output formats: YCbCr420 semi-planar,YCrCb420 semi-planar,

YCbCr422 semi-planar,YCrCb422 semi-planar,YUV420

基于Planar YUV422编码方案的支持下

颜色抑制技术
彩色校正技术
对比度增强与锐化效果
色调高级调节
二维空间降噪滤波器
色度分量降噪
区域基的AE/AF/AWB统计信息
抗闪烁检测统计信息
直方图统计信息

Audio Subsystem Audio Codec

Two audio digital-to-analog(DAC)

Channels supports both analog and digital volume controls. A low-noise analog microphone features an output bias. An analog low-power loop ensures a signal path from the microphone to the headphones.

outputs Supports Dynamic Range Controller adjusting the DAC playback

一个单个麦克风输入一个立体声线输出，并连接到两个音频的模拟-数字转换器（ADC）通道

- 92dB SNR@A-weight - Supports ADC Sample Rates from 8kHz to 48kHz

Supports Automatic Gain Control(AGC) and Dynamic Range Control(DRC)

adjusting the ADC recording input

External Peripherals USB

One USB 2.0 OTG controller with integrated

PHY Meets USB2.0 Standard and is Compatible with High-Speed Mode (HSM, 480 Mbit/s) and Full-Speed Mode (FSM, 12 Mbit/s).

Slow-Speed(LS,1.5 Mbit/s) when operating in host mode meets the requirements of the Improved Host Controller Interface (EHCI).

Specification, Version 1.0,and the Open Host

Controller Interface(OHCI) Specification,Version 1.0a for host

mode Up to 8 User-Configurable Endpoints in device

mode Supports point-to-point and point-to-multipoint transfer in both

host and peripheral mode

I2S/PCM

Compliant with standard Inter-IC sound(I2S) bus

This specification is consistent with left-aligned, right-aligned, PCM mode, and other similar configurations.

The Time Division Multiplexing (TDM) protocol operates in a fully duplex synchronous manner, with master/slave configuration modes available for selection. The system allows for adjustable audio sampling resolution ranging from 8 to 32 bits, providing flexibility in the quality and detail of audio processing.

Sample rate from 8 kHz to 192 kHz

Supports 8-bit u-law and 8-bit A-law companded sample

EMAC

Supports 10/100/1000 Mbit/s data transfer

rate Supports RGMII/MII/RMII interface

全双工和半双工操作用于链表描述结构，并支持标准型或巨无霸以太网的可变帧长度设置

frame sets with size limits not exceeding 16 KB incorporates a range of adaptable address filtering mechanisms

UART

Maximum of three UART controllers support 64-Byte transmit/receive data through FIFOs for every instance.

UART Compliant with industry-standard 16550 UARTs