Verilog 有符号数和无符号数的赋值和移位实验

 //验证算术右移和逻辑右移

    
 module test (
    
     input signed [7:0] A0,
    
     input signed [7:0] A1,
    
     input [7:0] B0,
    
     input [7:0] B1
    
 );
    
     wire [7:0] C0,C1,C2,C3;
    
     wire signed [7:0] D0,D1,D2,D3;
    
     wire [7:0] E0,E1,E2,E3;
    
     wire signed [7:0] F0,F1,F2,F3;
    
  
    
     assign C0 = B0 << 2;
    
     assign C1 = B0 >> 2;
    
     assign C2 = B0 <<< 2;
    
     assign C3 = B0 >>> 2;
    
  
    
     assign D0 = A0 << 2;
    
     assign D1 = A0 >> 2;
    
     assign D2 = A0 <<< 2;
    
     assign D3 = A0 >>> 2;
    
     
    
     assign E0 = A0 << 2;
    
     assign E1 = A0 >> 2;
    
     assign E2 = A0 <<< 2;
    
     assign E3 = A0 >>> 2;
    
  
    
     assign F0 = B0 << 2;
    
     assign F1 = B0 >> 2;
    
     assign F2 = B0 <<< 2;
    
     assign F3 = B0 >>> 2;
    
  
    
 endmodule
    
    
    
    
    java
    
    
![](https://ad.itadn.com/c/weblog/blog-img/images/2025-08-16/3pAPmk8ClWF29Gez5HJfhj0n1wvX.png)

 module test_tb(

    
   3.     );
    
     reg signed [7:0] A0,A1;
    
     reg [7:0] B0,B1;
    
  
    
     test test1(
    
     .A0(A0),
    
     .A1(A1),
    
     .B0(B0),
    
     .B1(B1)
    
     );
    
     initial begin
    
     A0 = 1101_0011;
    
     B0 = 1101_0011;
    
     A1 = -82;
    
     B1 = -82;
    
     #2
    
     $stop;
    
     end
    
 endmodule
    
    
    
    
    java
    
    
![](https://ad.itadn.com/c/weblog/blog-img/images/2025-08-16/oYq6IQ1Mbnh7wlpLXaRiWVjUxvTZ.png)

     A0 = -8'd250;

    
     B0 = -8'd250;
    
     A1 = 8'd250;
    
     B1 = 8'd250;
    
    
    
    

     A0 = -8'd25;

    
     B1 = 8'd128;
    
     B0 = A0;
    
     A1 = B1;